# Mapping to supplied PCS and USM design collateral

This package was aligned to the supplied Project Coherent Storage and Universal Storage Mesh artifacts.

## PCS mapping

- RDMA/RoCE-v2 traffic-class and congestion behavior maps to the PCS RDMA fabric ADRs and the pod-scale RDMA/RoCE-v2 tuning gates.
- GPU direct storage and accelerator kernel modeling maps to the PCS GPU-direct policy and heterogeneous GPU scheduler governance ADRs.
- OpenZFS TXG/writeback modeling maps to the OpenZFS/NVMe-oF/media layout ADR, including dirty data, sync pressure, checksums, compression, DPU/SPDK/NVMe-oF-adjacent paths, and durability separation from hot KV service behavior.
- Scaling decisions map to admission and scheduler governance signals: fabric latency, GPU utilization, TXG lag, and service p99s.

## USM mapping

- Metadata-domain and shard scaling maps to the metadata federation ADR.
- Per-class queueing and receiver-driven backpressure map to the queueing/backpressure ADR.
- Bulk transfer RDMA packet modeling maps to the bulk data movement ADR.
- Benchmark/test outputs map to the performance engineering record requirement: the package emits repeatable output files with configuration and observed metrics.

## Scope boundary

The model is an engineering simulator. It does not claim to be a cycle-accurate GPU simulator, a full OpenZFS implementation, or a real NIC firmware/RDMA stack. It captures the scaling algorithm and cross-domain feedback loops needed to reason about PCS and USM scaling under RoCE-v2, GPU, and OpenZFS pressure.
