PCSCoherent StorageV10 Download source
Menu
OverviewArchitectureSimulatorImpactADR browserGlossaryFAQDownload source

EXECUTABLE SYSTEMS MODEL / OCAML + SST BRIDGE

Trace the equation.
Then close the loop.

A deterministic event model now sits beside the conceptual design. Explore how RoCE packetization, GPU service time, OpenZFS transaction groups, metadata pressure, and bounded scaling actions influence one another.

MODEL WORKFLOW

Inputs become events, decisions, and evidence.

Select a stage to inspect its responsibility, emitted vocabulary, and implementation source. The divisions preserve the architecture-firm plan language: separate structures, joined by explicit circulation.

03 / SELECTED STAGE

Four model halls

Evaluates RoCE packet batches, GPU kernel phases, OpenZFS transaction groups, and USM metadata queues as separate but coupled systems.

EMITS OR PRODUCES
  • RdmaPacketBatch
  • GpuKernelSubmit
  • ZfsTxgWrite
  • BackpressureSignal
IMPLEMENTATION SOURCEsrc/storage_sim.ml / model_*

EQUATION WORKBENCH

Use the model as a transparent instrument.

Preset values come from the attached scenario JSON. Changes below are browser-side calculations of the documented equations; run the OCaml engine for multi-flow, rolling-window, and full-timeline evidence.

ACTIVE SCENARIOPCS / scale both

RoCE, GPU, and TXG pressure with horizontal and vertical actions enabled.

Seed
20260611
Duration
1.8 s
Tick
1000 us
Mode
both
scenarios/pcs/roce_gpu_txg_scale_both.json
E-01

RoCE-v2 packet path

LIVE / SOURCE-ALIGNED

Packetization establishes wire cost; aggregate work establishes utilization; utilization opens the ECN, queue, PFC, and retransmit regimes.

packets = ceil(payload / max(256, MTU - 86)) wire = payload + packets * (86 + 20) L_p99 = L_base + L_serial + L_queue + L_PFC + J_QP
01
Payload per packet8,914 B

MTU minus the modeled RoCE header, bounded at 256 B.

02
Packet and wire expansion89 packets / 777.2 KiB

Each packet adds 86 B of RoCE headers and 20 B of preamble/IFG.

03
Aggregate utilization89.1%

28 batches share 2 rail(s) during a 1000 us tick.

04
Latency composition46.31 us

5.14 us base + 31.83 us serialization + 0.00 us queue + 9.10 us PFC.

SOURCEsrc/storage_sim.ml / model_rdma

BUNDLED RUN EVIDENCE

Distinguish live math from completed runs.

The package includes complete generated PCS and USM scale-both output sets. The other three JSON presets are executable inputs without bundled output directories.

SCENARIO SUMMARY.JSONPCS / scale both12 rails / 800 Gb/s / 18 storage nodes / 288 GPUs
Requests94,441
Admission98.8%
RoCE p9945.83 us
TXG lag p9983.00 ms
Scale actions51

RUN THE ORIGINAL PACKAGE

From browser awareness to repeatable evidence.

The downloadable archive is preserved unchanged. It includes the OCaml source, compiled sandbox binary, scenarios, tests, diagrams, sample outputs, documentation, and SST-Core integration skeleton.

LOCAL WORKFLOW
make build
./bin/storage-sim pcs --scenario scenarios/pcs/roce_gpu_txg_scale_both.json --out out/pcs-both
make test
Download OCaml/RoCE/SST packageDownload SHA-256
OUTPUT CONTRACT
01summary.json
02timeline.csv
03rdma_packets.csv
04openzfs_txg.csv
05gpu_kernels.csv
06sst_components.csv
07sst_events.csv
08scaling_decisions.csv
REPEATABILITY EVIDENCEBuild, render, run, verify, hash.

The recorded sandbox test built the OCaml engine, rendered six PlantUML diagrams, generated both complete output sets, verified expected evidence, and reproduced deterministic hashes.

PCS a53a92b8239bd93ce7d2ae153b953ebf002e95916a074bf29c6bbb7813e3cd55USM 5fd40d74cebb7aefb886bc3e997ed4115a38b846f794be6d18682a6c109a0292

Scope boundary: this is an engineering simulator for scaling algorithms and cross-domain feedback loops. It is not a correctness proof, benchmark claim, cycle-accurate GPU model, complete OpenZFS implementation, or production RNIC firmware model.